The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to a method of forming three dimensional, integrated decoupling capacitors for integrated circuit devices.
Decoupling capacitors serve as a charge reservoir in integrated circuit (IC) devices to support instantaneous current surges that invariably accompany simultaneous circuit switching. In particular, decoupling capacitors are utilized in advanced electronic computing systems where they are employed both on-chip and across all levels of packaging, including single chip and multi chip modules, board and back plane. In addition, these passive components are typically required in the power distribution systems for ICs to reduce the simultaneous circuit switching noise, or ΔI (delta I) noise. However, the ability to support an adequate decoupling capacitance at high frequencies is of increasing concern in both on-chip and off-chip systems. The relentless scaling to ever-smaller device dimensions and faster circuit speeds at the chip level have driven the demand for higher packaging density, but they also drive a need for new solutions to the increasing decoupling dilemma.
More specifically, decoupling capacitors must not only possess sufficient capacitance, but also must be accessible in time scales comparable to the ever shorter clock cycle times, resulting from increasing circuit speeds. The increase in power efficiency required in microprocessor units (MPUs), especially for portable computing and communication needs, has further exacerbated the problem. By stabilizing the power supply voltage, system performance can be greatly improved. However, state-of-the-art MPUs can have up to 20% of the chip area devoted to decoupling capacitors, which increases cost and chip size.